Phase-locked loops are well known analog systems for recovering clock timing or clock frequency control. As a data transmission speed of a serial data link between a transmitter in one system or subsystem and a receiver in another system or subsystem increases, data recovery becomes increasingly more difficult. Typically there is a local time reference (e.g., a first clock) used by the transmitter to send the data stream and a separate local time reference (e.g., a second clock) used by the receiver. Accurate data extraction depends upon matching the receiver clock to the transmitting clock, which becomes more difficult as clock speeds increase and the operational power of the transmitter and receiver decreases. Factors that make extraction difficult include clock jitter and noise. Even as clock designs improve to reduce jitter, the increase of the clock speed continues to make jitter a significant factor in data extraction. Further, low power operational modes of the subsystems and supply and/or substrate coupling of multiple analog clock recovery circuits make noise an additional important factor.
For example, a high-speed serial link between two units (e.g., routers) may have a timing difference between local time references on each box be specified as 5000 parts per million which is 0.5 percent with 0.02 percent more common. These values represent a very large amount of jitter or phase/frequency mismatch that may have to be compensated for to accurately extract the serial data. Data extraction is further complicated when the transmitted data has several bit times in succession that have the same value, meaning that the receiver is unable to learn anything about the current clock value in the transmitted data.
Accordingly, what is needed is a system and method for tracking/adapting phase or frequency changes in an incoming serial data stream that may contain significant amounts of noise and/or jitter. The present invention addresses such a need.